1. Field of the Invention
This invention relates to alternating current powering of logic circuits which contain devices having bilateral gain characteristics. More particularly, it relates to an alternating current powering arrangement for Josephson junction logic circuits which have bilateral I.sub.g -I.sub.c characteristics. Because of this bilateral characteristic, any group of Josephson junctions may be actuated to carry out a logic function during one half cycle of an alternating current powering cycle and a completely different logic function during the other half of the alternating current powering cycle. A feature of this arrangement is that where the Josephson junction logic devices are latching in character, the passage of the alternating current power through zero every half cycle resets each logic device so that it is automatically prepared for the next logical operation. Where the devices in question are non-latching self-resetting occurs without the benefit of the zero axis crossing but, in the same way as with latching logic circuits, the next logical operation is carried out on the succeeding half cycle of the alternating current powering arrangement. Using the AC powering approach, combinatorial logic can be carried out in the usual manner. Thus, in order not to lose information as a result of latching or non-latching operation of a given logic circuit, data can be preserved by transferring the data to a temporary storage register or the like. In the present instance, this can be most conveniently done by the expedient of multiphase operation in conjunction with other logic circuits which can be activated by a differently phased alternating current to hold the information after the original logic circuit resets. In addition, the use of alternating current powering provides built-in timing with logic circuits disposed at the same distance from the source having the same phase.
2. Description of the Prior Art
There is no known prior art which shows alternating current powering of Josephson junction logic circuits in which the Josephson junctions have bilateral gain characteristics. In the usual situation, Josephson logic circuits or any other circuit, for that matter, having bilateral characteristics, are operated by applying pulses of a single polarity with timing of the various logical operations being controlled from a separate timing or synchronizing source. Known circuit arrangements which incorporate field effect transistors, for example are non-latching in character inasmuch as they revert to their initial state once a control signal has been removed from an associated gate electrode. While there is an analogous non-latching situation associated with Josephson junction logic circuits, there is no known analogy to Josephson junctions (which are at least three terminal devices) operating in the latching mode. In the latter mode, after a control signal has been removed, the Josephson junction logic device remains in a switched condition until the gate current through the device is dropped below a minimum value of current In the self-resetting mode, there is no requirement in the Josephson junction environment for changing the value of gate current applied, and where latching circuits have been utilized and the gate current must be reduced to some minimum value for resetting, the approach has been to use pulses of a single polarity which are returned to zero.
With respect to the particular logic circuits and shift registers of the present application, it should be appreciated that the logic circuits utilized herein do not depart in any substantial way from those found in the prior art. The shift register disclosed herein, that exemplifies the AC powering technique, from a circuit point of view, is similar to prior art circuits, but the latter are operated with pulses of a single polarity and incorporate different expedients than taught by the present application to prevent race conditions. Typical prior art logic circuits includes U.S. Pat. No. 3,458,735, issued July 29, 1969 to M. D. Fiske, which shows a series string of Josephson junctions which, when each is activated, provides a given voltage equal to the sum of the voltage drops of all the switched Josephson devices.
Prior art shift register arrangements which appear to be relevant include IBM Technical Disclosure Bulletin, Vol.15, No.12, May 1973, p.3663, entitled "Three Phase Shift Register" by H. Hamel et al. This article shows a number of logic circuits each of which is identical to that disclosed in the present disclosure. However, the circuit of the article utilizes the expedient of an additional phase to prevent a race condition and operates in a pulsed power mode.
IBM Technical Disclosure Bulletin, Vol.16, No.7, December 1973, p.2405, entitled "Sequential Switch Using Josephson Junctions" by M. Klein, shows a switching arrangement in which each stage of a sequential switch is substantially identical with the logic circuit of the present application. The article shows the use of an intermediate stage between two other stages which could be said to be operating using two phases. The circuit shown, however, operates so that the pulses which activate different stages are in a non-overlapping mode. Hence, the requirement for the intermediate storage stage.
IBM Technical Disclosure Bulletin, Vol.16, No.5, October 1973, p.1466, entitled "Pseudo-Single Phase Josephson Tunneling Device Shift Register" by Y. L. Yao, shows a shift register arrangement wherein a gate current pulse and its complement are applied to the gates of first and second circuits, respectively. This circuit, however, incorporates a delay to overcome the possibility that the presence of an output current might cause the succeeding device to switch because the complementary current to that circuit does not drop to zero instantaneously. This article recognizes the possibility for the occurrence of a race condition, but solves it by the expedient of the delay. There is no suggestion of the use of alternating current to power such arrangements.
IBM Technical Disclosure Bulletin, Vol.15, No.3, August 1972, p.899, entitled "Josephson Junction Circuits Having Magnetic Feedback", by H. H. Zappe, shows a shift register arrangement wherein alternate DC pulses are applied to alternately disposed Josephson junction connected to the same bus. In this arrangement, the alternate pulses are of the same polarity and the logic circuits, while all in parallel, do not use current diverted into a parallel branch to control a succeeding circuit.
IBM Technical Disclosure Bulletin, Vol.17, No.9, February 1975, p.2791, entitled "Three-Phase Josephson Tunneling Device Shift Register" by F. F. Fang et al, shows a shift register containing circuits almost identical with that shown in the present application. However, the article utilizes three phases, only two of which are available at any give time. This enables the data to transfer from one stage to the next only. Thus, a third phase and a third circuit are required to operate the shift register of the article. While the article suggests that clipped sine waves may be utilized, it should be noted that the clipped sine waves are utilized instead of square waves and the powering to the circuit is in essentially a pulsed mode. FIG. 2 of the reference clearly indicated that the gate current never goes below the zero axis. Further, only one logic operation per cycle can be achieved in this approach. Thus, there is no teaching or indication in this publication that bilateral operation of Josephson devices is envisioned, requiring the use of gate currents which are affirmatively alternating in character.
IBM Technical Disclosure Bulletin, Vol.12, No.3, August 1969, p.440, entitled "A Shift Register Employing Josephson Junctions" by L. M. Terman, shows a two phase shift register in which all the devices associated with a given phase are connected in series. The shift register utilizes four Josephson devices per stage and includes the use of circulating currents to control the condition of devices in a succeeding group. There is no indication of the use of alternating currents nor of the use of the bilateral characteristics of Josephson junctions.
U.S. Pat. No. 3,123,720 to V. L. Newhouse et al, issued Mar. 3, 1964, shows a cryotron shift register which is similar to the arrangement of the present application. The shift register uses three devices per stage and utilizes circulating current in a parallel output loop which remains after the gate current has been terminated. This, in turn, requires the use of a reset pulse and control line to destroy the circulating current in a first circuit. While the result achieved is the same as in all shift registers, there is no hint or suggestion in this reference for the use of alternating currents.
IBM Technical Disclosure Bulletin, Vol.16, No.12, May 1974, entitled "Clocking Power Supply for Josephson Tunneling Circuits by Capacitive Coupling" by W. Anacker shows the transformer coupling of pulsed voltages to a string of Josephson devices.
From the foregoing, it should be clear that, while specific logic circuits, specific shift registers and the use of clipped sine waves have been suggested by the prior art, none of the prior art logic circuits or shift registers takes advantage of the bilateral characteristics of Josephson devices to provide for the alternating current powering of both logic and shift register circuits which may be latching or non-latching in character.